ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 767

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 34-20. 2-bit Gray Up/Down Counter.
34.6.16
34.6.17
6500C–ATARM–8-Feb-11
TIOAx
TIOBx
DOWNx
Write Protection System
Fault Mode
TC_RCx
In order to bring security to the Timer Counter, a write protection system has been implemented.
The write protection mode prevent the write of TC_BMR, TC_FMR, TC_CMRx, TC_SMMRx,
TC_RAx, TC_RBx, TC_RCx registers. When this mode is enabled and one of the protected reg-
isters write, the register write request canceled.
Due to the nature of the write protection feature, enabling and disabling the write protection
mode requires the use of a security code. Thus when enabling or disabling the write protection
mode the WPKEY field of the TC_WPMR register must be filled with the “TIM” ASCII code (cor-
responding to 0x54494D) otherwise the register write will be canceled.
At anytime, the TC_RCx registers can be used to perform a comparison on the respective cur-
rent channel counter value (TC_CVx) with the value of TC_RCx register.
The CPCSx flags can be set accordingly and an interrupt can be generated.
This interrupt is processed but requires an unpredictable amount of time to be achieve the
required action.
It is possible to trigger the FAULT output of the TIMER1 with CPCS from TC_SR0 register
and/or CPCS from TC_SR1 register. Each source can be independently enabled/disabled by
means of TC_FMR register.
This can be useful to detect an overflow on speed and/or position when QDEC is processed and
to act immediately by using the FAULT output.
Figure 34-21. Fault Output Generation
TC_SR0 flag CPCS
TC_SR1 flag CPCS
TC_FMR / ENCF0
TC_FMR / ENCF1
WAVEx = GCENx =1
AND
AND
OR
FAULT (to PWM input)
SAM3S Preliminary
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