ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 501

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 28-3.
Notes:
Note:
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Offset
0x150
0x154
0x158
0x15C
0x160
0x164
0x0168
to
0x018C
1. Reset value of PIO_PSR depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
if an offset is not listed in the table it must be considered as reserved.
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
occurred.
Register
Parallel Capture Mode Register
Parallel Capture Interrupt Enable Register
Parallel Capture Interrupt Disable Register
Parallel Capture Interrupt Mask Register
Parallel Capture Interrupt Status Register
Parallel Capture Reception Holding Register
Reserved for PDC Registers
Register Mapping (Continued)
Name
PIO_PCMR
PIO_PCIER
PIO_PCIDR
PIO_PCIMR
PIO_PCISR
PIO_PCRHR
SAM3S Preliminary
SAM3S Preliminary
Read-write
Write-only
Write-only
Read-only
Read-only
Read-only
Access
0x00000000
0x00000000
0x00000000
0x00000000
Reset
–
–
501
501