R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 1177

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
23.1
The registers relating to the power-down mode are shown below. For details on the PLL control
register (PLLCR), see section 22.1.2, PLL Control Register (PLLCR).
• PLL control register (PLLCR)
• Standby control register (SBYCR)
• Module stop control register H (MSTPCRH)
• Module stop control register L (MSTPCRL)
• Extension module stop control register H (EXMSTPCRH)
• Extension module stop control register L (EXMSTPCRL)
• RAM module stop control register H (RMMSTPCRH)
• RAM module stop control register L (RMMSTPCRL)
23.1.1
SBYCR performs software standby mode control.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Bit
7
6
Bit Name
SSBY
OPE
Register Descriptions
Standby Control Register (SBYCR)
Initial Value
0
1
R/W
R/W
R/W
Description
Software Standby
This bit specifies the transition mode after
executing the SLEEP instruction
0: Shifts to sleep mode after the SLEEP
1: Shifts to software standby mode after the
This bit does not change from 1 when clearing the
software standby mode by using external
interrupts and shifting to normal operation. This bit
should be written 0 when clearing.
Output Port Enable
Specifies whether the output of the address bus
and bus control signals (CS0 to CS7, AS, RD,
HWR, LWR, UCAS*, LCAS*) is retained or set to
the high-impedance state in software standby
mode.
0: In software standby mode, address bus and bus
1: In software standby mode, address bus and bus
instruction is executed
SLEEP instruction is executed
control signals are high-impedance
control signals retain output state
Section 23 Power-Down Modes
Page 1147 of 1372