R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 67

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Type
Interrupt
signals
DMA
controller
(DMAC)
EXDMA
controller
(EXDMAC)
*
2
Symbol
NMI
IRQ15-A to
IRQ8-A*
IRQ7-A to
IRQ0-A
IRQ15-B to
IRQ8-B*
IRQ7-B to
IRQ0-B
DREQ1
DREQ0
TEND1
TEND0
DACK1
DACK0
EDREQ3
EDREQ2
ETEND3
ETEND2
EDACK3
EDACK2
EDRAK3
EDRAK2
2
2
Pin No.
H8S/2426, H8S/2426R
PLQP0144KA-A PTLG0145JB-A
40
86, 85,
106 to 104,
83 to 81
31 to 28,
136 to 133
58 to 51
38, 37,
61 to 59,
34, 33, 3
82
81
104
83
106
105
33
3
59
34
61
60
49
48
N1
H10, H12, C13,
D12, D10, J10,
K13, J12
J3, K2, J1, K4,
D4, C6, B5, A6
K7, L8, N7,
M7, N6, M6,
L7, L6
M2, N2, M8, N8,
K8, K3, L2, C2
K13, J12
D10, J10
C13
D12
L2
C2
K8
K3
M8
N8
L5
K6
H8S/2424
PLQP0120LA-A,
PLQP0120KA-A
32
⎯
29 to 26,
112 to 109
⎯
102 to 95
35
34
37
36
39
38
⎯
⎯
⎯
⎯
I/O
Input
Input
Input
Output
Output
Input
Output
Output
Output
Function
Nonmaskable interrupt request pin.
This pin should be fixed high when
not used.
These pins request a maskable
interrupt.
The input pins of IRQn-A and
IRQn-B are selected by the IRQ pin
select register (ITSR) of the
interrupt controller.
(n = 0 to 15 for the H8S/2426
Group and H8S/2426R Group, n =
0 to 7 for the H8S/2424 Group)
These signals request DMAC
activation.
These signals indicate the end of
DMAC data transfer.
DMAC single address transfer
acknowledge signals.
These signals request EXDMAC
activation.
These signals indicate the end of
EXDMAC data transfer.
EXDMAC single address transfer
acknowledge signals.
These signals notify an external
device of acceptance and start of
execution of a DMA transfer
request.
Section 1 Overview
Page 37 of 1372