R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 412

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
(6)
Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected.
Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level.
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Page 382 of 1372
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the write cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
φ
DREQ
Address
bus
DMA
control
Channel
DREQ Pin Low Level Activation Timing (Normal Mode)
Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
Idle
[1]
Request
of 2 cycles
release
Minimum
Bus
[2]
Read
[3]
Request clear period
Transfer source
DMA
read
Write
Transfer destination
Acceptance resumes
DMA
write
Idle
[4]
Request
of 2 cycles
Minimum
release
Bus
[5]
Read
[6]
Request clear period
Transfer source Transfer destination
H8S/2426, H8S/2426R, H8S/2424 Group
DMA
read
Write
REJ09B0466-0350 Rev. 3.50
Acceptance resumes
DMA
write
Idle
[7]
release
Jul 09, 2010
Bus