R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 932

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI, IrDA)
15.4.2
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched at the middle of each bit by sampling the data at
the rising edge of the 8th pulse of the basic clock as shown in figure 15.3. Thus the reception
margin in asynchronous mode is given by formula (1) below.
Where M: Reception Margin
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula
below.
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Page 902 of 1372
Internal base
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = { (0.5 –
N: Ratio of bit rate to clock (N = 16)
D: Clock duty cycle (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode
0
2N
8 clocks
Start bit
1
) – (L – 0.5) F –
16 clocks
7
⏐D – 0.5⏐
N
15 0
(1 + F) } × 100 [%]
D0
H8S/2426, H8S/2426R, H8S/2424 Group
7
REJ09B0466-0350 Rev. 3.50
... Formula (1)
Jul 09, 2010
15 0
D1