R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 327

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
(a)
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous
DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM
space read access can be enabled by setting the DRMI bit to 1. The conditions and number of
states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and
IDLC in RCR. Figure 6.91 shows an example of idle cycle operation when the DRMI bit is set to
1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after continuous synchronous
DRAM space read access even if bits ICIS1 and ICIS0 are set to 1.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Figure 6.91 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Precharge-sel
DQMU, DQML
Address bus
Normal space access after a continuous synchronous DRAM space read access
Data bus
CKE
CAS
RAS
WE
RD
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)
φ
PALL ACTV READ
Column
address
T
p
Continuous synchronous
DRAM space read
address
address
Row
Row
T
r
T
Column address 1
c1
T
cl
T
c2
Idle cycle
High
T
i
External space read
External address
External address
T
1
NOP
T
2
T
3
Continuous synchronous
DRAM space read
Section 6 Bus Controller (BSC)
T
i
Column address 2
T
c1
READ
T
Page 297 of 1372
Cl
NOP
T
c2