R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 607

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
10.5.3
PORT5 shows the pin states of port 5. PORT5 cannot be modified.
Note:
10.5.4
P5ODR specifies the output type of each port 5 pin.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Bit
7 to 4
3
2
1
0
Bit
7 to 4
3
2
1
0
*
Bit Name
⎯
P53
P52
P51
P50
Bit Name
⎯
P53ODR
P52ODR
P51ODR
P50ODR
Port 5 Register (PORT5)
Port 5 Open Drain Control Register (P5ODR)
Determined by the states of pins P53 to P50.
Initial Value
Undefined
⎯*
⎯*
⎯*
⎯*
Initial Value
All 0
0
0
0
0
R/W
R
R
R
R
R
R/W
⎯
R/W
R/W
R/W
R/W
Setting this bit to 1 makes the corresponding pin an
NMOS open-drain output pin, while clearing the bit
to 0 makes the corresponding pin a CMOS output
pin.
When BACK-B output is not selected, setting this bit
to 1 makes the corresponding pin an NMOS open-
drain output pin, while clearing the bit to 0 makes
the corresponding pin a CMOS output pin.
Setting this bit to 1 makes the corresponding pin an
NMOS open-drain output pin, while clearing the bit
to 0 makes the corresponding pin a CMOS output
pin.
When BREQO-B output is not selected, setting this
bit to 1 makes the corresponding pin an NMOS
open-drain output pin, while clearing the bit to 0
makes the corresponding pin a CMOS output pin.
Description
Reserved
If these bits are read, they will return an undefined
value.
If the P53 to P50 bits are read while a P5DDR bit is
set to 1, the corresponding P5DR value is read. If
this register is read while a P5DDR bit is cleared to
0, the corresponding pin state is read.
Description
Reserved
These bits are always read as 0. Only the initial
values should be written to these bits.
Section 10 I/O Ports
Page 577 of 1372