R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 993

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
16.3.3
ICMR controls the master mode wait and selects the number of transfer bits.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Bit
1
0
Bit
7
6
5, 4
3
Bit Name
IICRST
⎯
Bit Name
⎯
WAIT
⎯
BCWP
I
2
C Bus Mode Register (ICMR)
Initial Value
0
1
Initial Value
0
0
All 1
1
R/W
R/W
⎯
R/W
⎯
R/W
⎯
R/W
Description
IIC Control Part Reset
This bit resets control parts except for I
registers. If this bit is set to 1 when hang-up is
occurred because of communication failure during
I
setting ports and initializing registers.
Reserved
This bit is always read as 1.
Description
Reserved
The write value should always be 0.
Wait Insertion
This bit selects whether to insert a wait after data
transfer except for the acknowledge bit. When
WAIT is set to 1, after the fall of the clock for the
final data bit, low period is extended for two
transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively
with no wait inserted.
The setting of this bit is invalid in slave mode.
Reserved
These bits are always read as 1.
BC Write Protect
This bit controls the BC2 to BC0 modifications.
When modifying BC2 to BC0, this bit should be
cleared to 0 and use the MOV instruction.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
2
C operation, I
When writing, settings of BC2 to BC0 are
invalid.
2
C control part can be reset without
Section 16 I2C Bus Interface 2 (IIC2)
Page 963 of 1372
2
C