R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 363

MCU 256K FLASH 48K 144-LQFP

R4F24268NVFQV

Manufacturer Part Number
R4F24268NVFQV
Description
MCU 256K FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24268NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2426, H8S/2426R, H8S/2424 Group
• DMABCRL
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Bit
7
6
5
4
Bit Name
DTE1B
DTE1A
DTE0B
DTE0A
Initial Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Data Transfer Enable 1B
Data Transfer Enable 1A
Data Transfer Enable 0B
Data Transfer Enable 0A
If the DTE bit is cleared to 0 when DTIE = 1, the
DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt
request to the CPU or DTC.
When DTE = 0, data transfer is disabled and the
DMAC ignores the activation source selected by
the DTF3 to DTF0 bits in DMACR.
When DTE = 1, data transfer is enabled and the
DMAC waits for a request by the activation source
selected by the DTF3 to DTF0 bits in DMACR.
When a request is issued by the activation source,
DMA transfer is executed.
[Clearing conditions]
[Setting condition]
When 1 is written to the DTE bit after reading DTE
= 0
When initialization is performed
When the specified number of transfers have
been completed in a transfer mode other than
repeat mode
When 0 is written to the DTE bit to forcibly
suspend the transfer, or for a similar reason
Section 7 DMA Controller (DMAC)
Page 333 of 1372

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