R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 252

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.7
In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing
performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM
space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst
operation is also possible, using fast page mode.
Note: The DRAM interface is not supported by the 5-V version.
6.7.1
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.5.
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2
to 5), and continuous area (areas 2 to 5).
Table 6.5
Note:
With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait
states, etc.) for continuous DRAM space conform to the settings for area 2.
6.7.2
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table
6.6 shows the relation between the settings of MXC2 to MXC0 and the shift size.
The MXC2 bit should be cleared to 0 when the DRAM interface is used.
Page 222 of 1372
RMTS2
0
1
*
DRAM Interface
Setting DRAM Space
Address Multiplexing
Reserved (setting prohibited) in the H8S/2426 Group and H8S/2424 Group.
RMTS1
0
1
0
1
Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space
RMTS0
0
1
0
1
0
1
1
Area 5
Normal space
Normal space
DRAM space
Continuous synchronous DRAM space*
Mode register settings of synchronous DRAM*
Reserved (setting prohibited)
Continuous
DRAM space
Area 4
Normal space
Normal space
DRAM space
Continuous
DRAM space
H8S/2426, H8S/2426R, H8S/2424 Group
Area 3
Normal space
DRAM space
DRAM space
Continuous
DRAM space
REJ09B0466-0350 Rev. 3.50
Area 2
DRAM space
DRAM space
DRAM space
Continuous
DRAM space
Jul 09, 2010