DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 281

IC H8S MCU FLASH 128K 100-QFP

DF2148ATE20

Manufacturer Part Number
DF2148ATE20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2148ATE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
Host Interface, I²C, IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148ATE20
HD64F2148ATE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2148ATE20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Port 3 Data Register (P3DR)
P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P37 to P30).
If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly,
regardless of the actual pin states. If a port 3 read is performed while P3DDR bits are cleared to 0,
the pin states are read.
P3DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port 3 MOS Pull-Up Control Register (P3PCR)
P3PCR is an 8-bit readable/writable register that controls the port 3 built-in MOS input pull-ups
on a bit-by-bit basis.
In modes 2 and 3 (when EXPE = 0), the MOS input pull-up is turned on when a P3PCR bit is set
to 1 while the corresponding P3DDR bit is cleared to 0 (input port setting).
P3PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
The MOS input pull-up function cannot be used in slave mode (when the host interface is
enabled).
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
P37PCR
P37DR
R/W
R/W
7
0
7
0
P36PCR
P36DR
R/W
R/W
6
0
6
0
P35PCR
P35DR
R/W
R/W
5
0
5
0
P34PCR
P34DR
R/W
R/W
4
0
4
0
Rev. 4.00 Sep 27, 2006 page 235 of 1130
P33PCR
P33DR
R/W
R/W
3
0
3
0
P32PCR
P32DR
R/W
R/W
2
0
2
0
P31PCR
P31DR
Section 8 I/O Ports
R/W
R/W
REJ09B0327-0400
1
0
1
0
P30PCR
P30DR
R/W
R/W
0
0
0
0

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