DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 33

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

9.3
Section 10 14-Bit PWM Timer (PWMX)
10.1 Overview........................................................................................................................... 291
10.2 Register Descriptions ........................................................................................................ 294
10.3 Bus Master Interface ......................................................................................................... 299
10.4 Operation .......................................................................................................................... 302
Section 11 16-Bit Free-Running Timer
11.1 Overview........................................................................................................................... 307
11.2 Register Descriptions ........................................................................................................ 311
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10 Module Stop Control Register (MSTPCR) .......................................................... 288
Operation .......................................................................................................................... 289
9.3.1
10.1.1 Features................................................................................................................ 291
10.1.2 Block Diagram ..................................................................................................... 292
10.1.3 Pin Configuration................................................................................................. 293
10.1.4 Register Configuration......................................................................................... 293
10.2.1 PWM (D/A) Counter (DACNT) .......................................................................... 294
10.2.2 D/A Data Registers A and B (DADRA and DADRB)......................................... 295
10.2.3 PWM D/A Control Register (DACR) .................................................................. 296
10.2.4 Module Stop Control Register (MSTPCR) .......................................................... 298
11.1.1 Features................................................................................................................ 307
11.1.2 Block Diagram ..................................................................................................... 308
11.1.3 Input and Output Pins .......................................................................................... 309
11.1.4 Register Configuration......................................................................................... 310
11.2.1 Free-Running Counter (FRC) .............................................................................. 311
11.2.2 Output Compare Registers A and B (OCRA, OCRB) ......................................... 311
11.2.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 312
11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF) ............................... 313
11.2.5 Output Compare Register DM (OCRDM) ........................................................... 314
11.2.6 Timer Interrupt Enable Register (TIER) .............................................................. 314
PWM Register Select (PWSL)............................................................................. 282
PWM Data Registers (PWDR0 to PWDR15) ...................................................... 284
PWM Data Polarity Registers A and B (PWDPRA and PWDPRB).................... 284
PWM Output Enable Registers A and B (PWOERA and PWOERB) ................. 285
Peripheral Clock Select Register (PCSR) ............................................................ 286
Port 1 Data Direction Register (P1DDR)............................................................. 286
Port 2 Data Direction Register (P2DDR)............................................................. 287
Port 1 Data Register (P1DR)................................................................................ 287
Port 2 Data Register (P2DR)................................................................................ 287
Correspondence between PWM Data Register Contents
and Output Waveform.......................................................................................... 289
......................................................................... 307
..................................................................... 291
Rev. 4.00 Sep 27, 2006 page xxxi of xliv