DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 433

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Bits 1 and 0—Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits
select the signal source for the CLO signal (clamp waveform).
13.2.4
SEDGR is an 8-bit readable/writable register used to detect a rising edge on the timer connection
input pins and the occurrence of 2fH modification, and to determine the phase of the IVI and IHI
signals.
The upper 6 bits of SEDGR are initialized to 0 by a reset and in hardware standby mode. The
initial value of the lower 2 bits is undefined, since it depends on the pin states.
Bit 6
ISGENE
0
1
Bit
Initial value
Read/Write
Notes: 1. Only 0 can be written, to clear the flags.
Edge Sense Register (SEDGR)
2. The initial value is undefined since it depends on the pin states.
Bit 1
CLMOD1
0
1
0
1
VEDG
R/(W)
7
0
*
1
Bit 0
CLMOD2
0
1
0
1
0
1
0
1
HEDG
R/(W)
6
0
*
1
CEDG
R/(W)
Description
The CL1 signal is selected
The CL2 signal is selected
The CL3 signal is selected
The CL4 signal is selected
5
0
*
1
HFEDG
R/(W)
4
0
*
1
Rev. 4.00 Sep 27, 2006 page 387 of 1130
VFEDG
R/(W)
3
0
*
1
PREQF
R/(W)
Section 13 Timer Connection
2
0
*
1
—*
IHI
REJ09B0327-0400
R
1
2
(Initial value)
—*
IVI
R
0
2