DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 440

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 13 Timer Connection
13.3.3
The timer connection facility, TMR1, and the free-running timer (FRT) can be used to measure the
period of an IHI signal divided waveform. Since TMR1 can be cleared by a rising edge of inverted
IVI signal, the rise and fall of the IHI signal divided waveform can be virtually synchronized with
the IVI signal. This enables period measurement to be carried out efficiently.
To measure the period of an IHI signal divided waveform, TCNT in TMR1 is set to count the
external clock (IHI signal) pulses and to be cleared on the rising edge of the external reset signal
(inverted IVI signal). The value to be used as the division factor is written in TCORA, and the
TMO output method is specified by the OS bits in TCSR. Examples of TCR and TCSR settings
are shown in table 13.5, and the timing chart for measurement of the IVI signal and IHI signal
divided waveform periods is shown in figure 13.5. The period of the IHI signal divided waveform
is given by (ICRD(3) – ICRD(2))
Rev. 4.00 Sep 27, 2006 page 394 of 1130
REJ09B0327-0400
TICR+TCORC
Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)
IHI signal
CL1 signal
CL2 signal
TCNT
TCORA
IHI signal
CL3 signal
TCNT
TICR
Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal)
Measurement of 8-Bit Timer Divided Waveform Period
the resolution.