DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 29

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Overview........................................................................................................................... 113
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 117
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
Interrupt Sources............................................................................................................... 126
5.3.1
5.3.2
5.3.3
Address Breaks ................................................................................................................. 132
5.4.1
5.4.2
5.4.3
5.4.4
Interrupt Operation............................................................................................................ 135
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
Usage Notes ...................................................................................................................... 146
5.6.1
5.6.2
5.6.3
DTC Activation by Interrupt............................................................................................. 148
5.7.1
5.7.2
5.7.3
Features................................................................................................................ 113
Block Diagram ..................................................................................................... 114
Pin Configuration................................................................................................. 115
Register Configuration......................................................................................... 116
System Control Register (SYSCR) ...................................................................... 117
Interrupt Control Registers A to C (ICRA to ICRC)............................................ 118
IRQ Enable Register (IER) .................................................................................. 119
IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 119
IRQ Status Register (ISR).................................................................................... 120
Keyboard Matrix Interrupt Mask Register (KMIMR) ......................................... 122
Keyboard Matrix Interrupt Mask Register (KMIMRA)....................................... 122
Address Break Control Register (ABRKCR)....................................................... 124
Break Address Registers A, B, C (BARA, BARB, BARC)................................. 125
External Interrupts ............................................................................................... 126
Internal Interrupts................................................................................................. 128
Interrupt Exception Vector Table ........................................................................ 128
Features................................................................................................................ 132
Block Diagram ..................................................................................................... 132
Operation ............................................................................................................. 133
Usage Notes ......................................................................................................... 133
Interrupt Control Modes and Interrupt Operation ................................................ 135
Interrupt Control Mode 0 ..................................................................................... 138
Interrupt Control Mode 1 ..................................................................................... 140
Interrupt Exception Handling Sequence .............................................................. 143
Interrupt Response Times .................................................................................... 145
Contention between Interrupt Generation and Disabling..................................... 146
Instructions That Disable Interrupts..................................................................... 147
Interrupts during Execution of EEPMOV Instruction.......................................... 147
Overview.............................................................................................................. 148
Block Diagram ..................................................................................................... 148
Operation ............................................................................................................. 149
.......................................................................................... 113
Rev. 4.00 Sep 27, 2006 page xxvii of xliv