DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 599

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

I
(Master transmit mode)
Other device
(Master transmit mode)
I
(Slave receive mode)
2
2
Notes on Arbitration Lost in Master Mode
The I
arbitration is lost in master mode and a transition to slave receive mode is automatically
carried out.
When arbitration is lost not in the first frame but in the second frame or subsequent frame,
transmit/receive data that is not an address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the address in the SAR or SARX
register, the I
figure 16.24.)
In multi-master mode, a bus conflict could happen. When The I
master mode, check the state of the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or subsequent frame, take
avoidance measures.
Though it is prohibited in the normal I
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit
when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1
according to the order below.
(a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
(b) Set the MST bit to 1.
C bus interface
C bus interface
the MST bit.
2
C bus interface recognizes the data in transmit/receive frame as an address when
Figure 16.24 Diagram of Erroneous Operation when Arbitration is Lost
2
C bus interface erroneously recognizes that the address call has occurred. (See
S
S
S
• Receive address is ignored
SLA
SLA
SLA
Transmit data match
Transmit timing match
R/W
R/W
R/W
2
C protocol, the same problem may occur when the MST
A
A
A
• Arbitration is lost
• The AL flag in ICSR is set to 1
• Automatically transferred to slave
• Receive data is recognized as
• When the receive data matches to
an address
the address set in the SAR or SARX
register, the I
as a slave device
receive mode
SLA
DATA1
DATA2
Rev. 4.00 Sep 27, 2006 page 553 of 1130
Transmit data does not match
2
Section 16 I
C bus interface operates
R/W
2
A
A
C bus interface is operated in
2
C Bus Interface [Option]
DATA4
DATA3
REJ09B0327-0400
Data contention
A
A