DF2148ATE20 Renesas Electronics America, DF2148ATE20 Datasheet - Page 437

• Manufacturer Part Number: DF2148ATE20
• Description: IC H8S MCU FLASH 128K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2148ATE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: Host Interface, I²C, IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2148ATE20; HD64F2148ATE20

MSTPCRH Bit 4—Module Stop (MSTP12): Specifies 8-bit timer channel 0 and 1 module stop
mode.
MSTPCRH Bit 0—Module Stop (MSTP8): Specifies 8-bit timer channel X and Y and timer
connection module stop mode.
13.3
13.3.1
The timer connection facility and TMRX can be used to decode a PWM signal in which 0 and 1
are represented by the pulse width. To do this, a signal in which a rising edge is generated at
regular intervals must be selected as the IHI signal.
The timer counter (TCNT) in TMRX is set to count the internal clock pulses and to be cleared on
the rising edge of the external reset signal (IHI signal). The value to be used as the threshold for
deciding the pulse width is written in TCORB. The PWM decoder contains a delay latch which
uses the IHI signal as data and compare-match signal B (CMB) as a clock, and the state of the IHI
signal (the result of the pulse width decision) at the compare-match signal B timing after TCNT is
reset by the rise of the IHI signal is output as the PDC signal. The pulse width setting using
TICRR and TICRF of TMRX can be used to determine the pulse width decision threshold.
Examples of TCR and TCORB settings are shown in tables 13.3 and 13.4, and the timing chart is
shown in figure 13.2.
MSTPCRH
Bit 4
MSTP12
0
1
MSTPCRH
Bit 0
MSTP8
0
1
Operation
PWM Decoding (PDC Signal Generation)
Description
8-bit timer channel 0 and 1 module stop mode is cleared
8-bit timer channel 0 and 1 module stop mode is set
Description
8-bit timer channel X and Y and timer connection module stop mode is cleared
8-bit timer channel X and Y and timer connection module stop mode is
set
Rev. 4.00 Sep 27, 2006 page 391 of 1130
Section 13 Timer Connection
REJ09B0327-0400
(Initial value)
(Initial value)