UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 145
UPSD3433E-40U6
Manufacturer Part Number
UPSD3433E-40U6
Description
MCU 8BIT 8032 128KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3422EV-40U6.pdf
(300 pages)
Specifications of UPSD3433E-40U6
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4907
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPSD3433E-40U6
Manufacturer:
DENSO
Quantity:
83
Company:
Part Number:
UPSD3433E-40U6
Manufacturer:
STMicroelectronics
Quantity:
10 000
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UPSD3422, UPSD3433, UPSD3434, UPSD3454
24.4
Figure 46. SPI transmit operation example
SPI SFR registers
Six SFR registers control the SPI interface:
●
●
●
●
●
●
The SPI interface functional block diagram
transmit and receive data paths are double-buffered, meaning that continuous transmitting
or receiving (back-to-back transfer) is possible by reading from SPIRDR or writing data to
SPITDR while shifting is taking place. There are a number of flags in the SPISTAT register
that indicate when it is full or empty to assist the 8032 MCU in data flow management. When
enabled, these status flags will cause an interrupt to the MCU.
SPICON0
SPICON1
SPITDR (SFR D4h, Write only) holds byte to transmit
SPIRDR (SFR D5h, Read only) holds byte received
SPICLKD
SPISTAT
SPIINTR
(SPO=0)
(SPO=1)
SPICLK
SPICLK
SPITXD
SPISEL
interrupt requested
TEISF
BUSY
SPITDR Empty
TISF
(Table 95 on page
(Table
(Table
(Table
93) for clock divider
89) for interface control
91) for interrupt control
write data in TDR
Interrupt handler
Bit0
Bit1
149) holds interface status
1 frame
interrupt requested
SPITDR Empty
(Figure
Bit7
SPI (synchronous peripheral interface)
47) shows these six SFRs. Both the
Bit0
Bit1
interrupt requested
Transmit End
Bit7
AI07854
145/300
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