UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 158
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
UPSD3433E-40U6
Manufacturer Part Number
UPSD3433E-40U6
Description
MCU 8BIT 8032 128KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3422EV-40U6.pdf
(300 pages)
Specifications of UPSD3433E-40U6
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4907
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPSD3433E-40U6
Manufacturer:
DENSO
Quantity:
83
Company:
Part Number:
UPSD3433E-40U6
Manufacturer:
STMicroelectronics
Quantity:
10 000
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USB interface
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Figure 53. FIFOs with no pairing
●
Pairing FIFOs example
Now assume that IN Endpoint1 and Endpoint2 FIFOs are paired for double buffering
and the same 1024 bytes of data are to be transferred to the host. As in the non-
pairing example, the CPU loads the IN Endpoint0 FIFO with 64 bytes of data. Instead
of having to wait for the SIE to transfer the 64 bytes of data to the host, the CPU can
write another 64 bytes of data to IN Endpoint0 FIFO. While the CPU is writing the
second packet of 64 bytes of data into the FIFO, the SIE is sending the first packet of
64 bytes of data to the host. After the CPU has written the second packet of 64 bytes to
the FIFO, it waits a shorter amount of time for the SIE to complete sending the first
packet of data since they were working concurrently. As soon as the first packet is sent
by the SIE, the second packet is immediately available to be sent by the SIE since the
FIFO was already loaded by the MCU. Also, after the first packet is sent by the SIE, the
alternate FIFO is available for the MCU to load the third packet of 64 bytes of data.
With double buffering, the MCU is able to always have a FIFO loaded and ready with
data to be sent by the SIE when the host sends an IN token maximizing the data
transfer rate.
interface
engine
Serial
Endpoint0
Endpoint1
Endpoint2
Endpoint3
Endpoint4
Endpoint4
Endpoint3
Endpoint2
Endpoint1
Endpoint0
Endpoint0 OUT FIFO
Endpoint1 OUT FIFO
Endpoint2 OUT FIFO
Endpoint3 OUT FIFO
Endpoint4 OUT FIFO
Endpoint4 IN FIFO
Endpoint3 IN FIFO
Endpoint2 IN FIFO
Endpoint1 IN FIFO
Endpoint0 IN FIFO
UPSD3422, UPSD3433, UPSD3434, UPSD3454
interface
FIFO
logic
XDATA
CTRL
USB SFRs
MCU
8032
AI10493b
R
S
F
b
u
s
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