UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 164

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

USB interface
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Table 105. UIE0 register bit definition
●
●
Table 106. USB IN FIFO interrupt enable register (UIE1 0E5h, reset value 00h)
Table 107. UIE1 register bit definition
Table 108. USB OUT FIFO interrupt enable register (UIE2 0E6h, reset value 00h)
Bit 7
Bit 7
Bit
Bit
USB IN FIFO interrupt enable register (UIE1)
When an endpoint’s IN FIFO has been successfully sent to the host with an IN
transaction, the FIFO becomes empty. The UIE1 register is used to enable each
endpoint’s IN FIFO interrupt
USB OUT FIFO interrupt enable register (UIE1)
When an endpoint’s OUT FIFO has been filled by an OUT transaction from the host,
the FIFO becomes full. The UIE2 register is used to enable each endpoint’s OUT FIFO
interrupt
7
6
5
4
3
2
1
0
–
7
6
5
4
3
2
1
0
–
SUSPEND
RESUMIE
Symbol
Symbol
(Table
EOPIE
RSTIE
IN4IE
IN3IE
IN2IE
IN1IE
IN0IE
Bit 6
Bit 6
IE
–
–
–
–
–
–
–
–
–
108).
Bit 5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 5
–
–
–
–
–
–
–
–
–
(Table
Reserved
Reserved
Reserved
Reserved
Enable the USB Reset interrupt
Enable the USB Suspend interrupt
Enable the USB EOP interrupt
Enable the USB Resume interrupt
Reserved
Reserved
Reserved
Enable Endpoint 4 IN FIFO interrupt
Enable Endpoint 3 IN FIFO interrupt
Enable Endpoint 2 IN FIFO interrupt
Enable Endpoint 1 IN FIFO interrupt
Enable Endpoint 0 IN FIFO interrupt
OUT4IE
IN4IE
Bit 4
Bit 4
106).
UPSD3422, UPSD3433, UPSD3434, UPSD3454
IN3IE
OUT3IE
Bit 3
Bit 3
Definition
Definition
IN2IE
Bit 2
OUT2IE
Bit 2
IN1IE
Bit 1
OUT1IE
Bit 1
OUT0IE
IN0IE
Bit 0
Bit 0