UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 148

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

SPI (synchronous peripheral interface)
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Table 90.
Table 91.
Table 92.
Table 93.
DIV128
Bit 7
Bit 7
7-4
Bit
Bit
3
2
1
0
–
3
2
1
0
SPICON0 register bit definition (continued)
SPICON1: SPI interface control register 1 (SFR D7h, reset value 00h)
SPICON1 register bit definition
SPICLKD: SPI prescaler (clock divider) register (SFR D2h, reset value
04h)
Symbol
Symbol
RORIE
DIV64
SSEL
FLSB
TEIE
SPO
Bit 6
Bit 6
RIE
TIE
–
–
–
DIV32
Bit 5
Bit 5
R/W
R/W
RW
RW
RW
RW
RW
RW
–
–
–
–
Slave Selection
0 = SPISEL output pin is constant logic '1' (slave device not
selected)
1 = SPISEL output pin is logic '0' (slave device is selected)
during data transfers
First LSB
0 = Transfer the most significant bit (MSB) first
1 = Transfer the least significant bit (LSB) first
Sampling Polarity
0 = Sample transfer data at the falling edge of clock (SPICLK
is '0' when idle)
1 = Sample transfer data at the rising edge of clock (SPICLK is
'1' when idle)
Reserved
Reserved
Transmission End Interrupt Enable
0 = Disable Interrupt for Transmission End
1 = Enable Interrupt for Transmission End
Receive Overrun Interrupt Enable
0 = Disable Interrupt for Receive Overrun
1 = Enable Interrupt for Receive Overrun
Transmission Interrupt Enable
0 = Disable Interrupt for SPITDR empty
1 = Enable Interrupt for SPITDR empty
Reception Interrupt Enable
0 = Disable Interrupt for SPIRDR full
1 = Enable Interrupt for SPIRDR full
DIV16
Bit 4
Bit 4
–
UPSD3422, UPSD3433, UPSD3434, UPSD3454
TEIE
DIV8
Bit 3
Bit 3
Definition
Definition
RORIE
DIV4
Bit 2
Bit 2
Bit 1
Bit 1
TIE
–
Bit 0
Bit 0
RIE
–