UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 162

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

USB interface
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Endpoint FIFO pairing
Endpoint FIFOs can be paired for double buffering to provide an efficient method for bulk
data transfers. With double buffering enabled, the MCU can operate on one data packet
while another is being transferred over USB.
When two FIFOs are paired, the active FIFO is automatically toggled by the update of
USIZE. The MCU must only use the odd numbered endpoint FIFO when paired in order to
access the active FIFO. For example, if endpoints 3 and 4 OUT FIFOs are paired, the active
FIFO is accessed via endpoint 3’s OUT FIFO (see
Table 100. USB device address register (UADDR 0E2h, reset value 00h)
Table 101. UADDR register bit definition
Table 102. Pairing control register (UPAIR 0E3h, reset value 00h)
Table 103. UPAIR register bit definition
Bit 7
Bit
6:0
–
7
Bit 7
Bit
–
7
6
5
4
3
2
1
0
USBADDR
Symbol
Bit 6
PR3OUT
PR1OUT
–
Symbol
PR3IN
PR1IN
Bit 6
–
–
–
–
–
Bit 5
R/W
R/W
–
Bit 5
R/W
R/W
R/W
R/W
R/W
–
–
–
–
–
Reserved
USB Address of the device.
These bits are cleared with a Hardware RESET. When a USB
RESET is detected, the address register should be cleared.
Reserved
Reserved
Reserved
Reserved
Setting this bit enables double buffering of the OUT FIFOs for
Endpoints 3 and 4. Access to the double buffered FIFOs is
through Endpoint3’s OUT FIFO.
Setting this bit enables double buffering of the OUT FIFOs for
Endpoints 1 and 2. Access to the double buffered FIFOs is
through Endpoint1’s OUT FIFO.
Setting this bit enables double buffering of the IN FIFOs for
Endpoints 3 and 4. Access to the double buffered FIFOs is
through Endpoint3’s IN FIFO.
Setting this bit enables double buffering of the IN FIFOs for
Endpoints 1 and 2. Access to the double buffered FIFOs is
through Endpoint1’s IN FIFO.
Bit 4
Bit 4
–
UPSD3422, UPSD3433, UPSD3434, UPSD3454
USBADDR[6:0]
PR3OUT
Bit 3
Bit 3
Table
102).
Definition
Definition
PR1OUT
Bit 2
Bit 2
Bit 1
PR3IN
Bit 1
PR1IN
Bit 0
Bit 0