UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 254

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UPSD3433E-40U6

Manufacturer Part Number
UPSD3433E-40U6
Description
MCU 8BIT 8032 128KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet

Specifications of UPSD3433E-40U6

Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4907

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPSD3433E-40U6
Manufacturer:
DENSO
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83
Part Number:
UPSD3433E-40U6
Manufacturer:
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Quantity:
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0
PSD module
28.5.57
28.5.58
28.5.59
254/300
The default state of the Turbo Bit is logic '0,' meaning Turbo mode is on by default (after
power-up and reset conditions) until it is turned off by the 8032 writing to PMMR0.
PLD current consumption
Figure 95 on page 265
show the relationship between PLD current consumption and the composite frequency of all
the transitions on PLD inputs, indicating that a higher input frequency results in higher
current consumption.
Current consumption of the PLDs have a DC component and an AC component. Both need
to be considered when calculating current consumption for a specific PLD design. When
Turbo mode is on, there is a linear relationship between current and frequency, and there is
a substantial DC current component consumed by the PSD module when there are no
transitions on PLD inputs (composite frequency is zero). The magnitude of this DC current
component is directly proportional to how many product terms are used in the equations of
both PLDs. PSDsoft Express generates a “fitter” report that specifies how many product
terms were used in a design out of a total of 186 available product terms.
page 265
product terms used, and another with 25% of the 186 product terms used.
Turbo mode current consumption
To determine the AC current component of the specific PLD design with Turbo mode on, the
user will have to interpolate from the graph, given the number of product terms specified in
the fitter report, and the estimated composite frequency of PLD input signal transitions. For
the DC component (y-axis crossing), the user can calculate the number by multiplying the
number of product terms used (from fitter report) times the DC current per product term
specified in the DC specifications for the PSD module. The total PLD current usage is the
sum of its AC and DC components.
Non-turbo mode current consumption
Notice in
the DC current consumption is “zero” (just standby current) when the composite frequency
of PLD input transitions is zero (no input transitions). Now moving up the frequency axis to
consider the AC current component, current consumption remains considerably less than
Turbo mode until PLD input transitions happen so rapidly that the PLDs do not have time to
latch their outputs and go to standby between the transitions anymore. This is where the
lines converge on the graphs, and current consumption becomes the same for PLD input
transitions at this frequency and higher regardless if Turbo mode is on or off. To determine
the current consumption of the PLDs with Turbo mode off, extrapolate the AC component
from the graph based on number of product terms and input frequency. The only DC
component in non-Turbo mode is the PSD module standby current.
The key to reducing PLD current consumption is to reduce the composite frequency of
transitions on the PLD input bus, moving down the frequency scale on the graphs. One way
to do this is to carefully select which signals are entering PLD inputs, not selecting high
frequency signals if they are not used in PLD equations. Another way is to use PLD
“Blocking Bits” to block certain signals from entering the PLD input bus.
Figure 95 on page 265
and
Figure 96 on page 266
and
Figure 96 on page 266
and
Figure 96 on page 266
both give two examples, one with 100% of the 186
UPSD3422, UPSD3433, UPSD3434, UPSD3454
(5 V and 3.3 V devices respectively)
that when Turbo mode is off,
Figure 95 on

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