UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 251

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.5.54
are driving the address lines. The PLDs will also stay in standby mode if the PLDs are in
non-Turbo mode and if all other PLD inputs (non-address signals) are static.
However, if the ALE signal has a transition before the APD counter reaches max count, the
APD counter is cleared to zero and the PDN signal will not go active, preventing power-
down mode. To prevent unwanted APD time-outs during normal 8032 operation (not
sleeping), it is important to choose a clock frequency for CLKIN that will NOT produce 15 or
more pulses within the longest period between ALE transitions. A 32768 Hz clock signal is
quite often an ideal frequency for CLKIN and APD, and this frequency is often available on
external supervisor or real-time clock devices.
The “PDN” power-down indicator signal is available to the PLD input bus to use in any PLD
equations if desired. The user may want to send this signal as a PLD output to an external
device to indicate the PSD module is in power-down mode. PSDsoft Express automatically
includes the “PDN” signal in the DPLD chip select equations for FSx, CSBOOTx, RS0, and
CSIOP.
The following should be kept in mind when the PSD module is in power-down mode:
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The APD counter will count whenever Bit 1 of csiop PMMR0 register is set to logic '1,' and
when the ALE signal is steady at either logic ’1’ or logic ’0’ (not transitioning).
page 253
PSDsoft Express to enable APD mode is to select the pin function “Common Clock Input,
CLKIN” before programming with JTAG.
Forced power-down (FDP)
An alternative to APD is FPD. The resulting power-savings is the same, but the PDN signal
in
firmware sets the FORCE_PD Bit to logic '1' in the csiop register PMMR3 (Bit 1). FPD will
override APD counter activity when FORCE_PD is set. No external clock source for the APD
counter is needed. The FORCE_PD Bit is cleared only by a reset condition.
Caution must be used when implementing FPD because code memory goes off-line as
soon as PSD module Power-Down mode is entered, leaving the MCU with no instruction
stream to execute.
The MCU module must put itself into Power-Down mode after it puts the PSD module into
Power-Down Mode. How can it do this if code memory goes off-line? The answer is the Pre-
Fetch Queue (PFQ) in the MCU module. By using the instruction scheme shown in the 8051
Figure 88 on page 252
8032 address and data bus signals are blocked from all memories and both PLDs.
The PSD module comes out of power-down mode when: ALE starts pulsing again, or
the CSI input on pin PD2 transitions from logic ’1’ to logic '0,' or the PSD module reset
signal, RST, transitions from logic ’0’ to logic '1.'
Various signals can be blocked (prior to power-down mode) from entering the PLDs by
using “blocking bits” in csiop PMMR registers.
The Flash memory enters standby mode, and the state of the PLDs and I/O Ports are
unchanged (if no PLD inputs change).
power-down mode on I/O pins while in various operating modes.
The 8032 Ports 1,3, and 4 on the MCU module are not affected at all by power-down
mode in the PSD module.
Power-down standby current given in the AC specifications for PSD module assume
there are no transitions on any unblocked PLD input, and there are no output pins
driving any loads.
shows the flow leading up to power-down mode. The only action required in
is set and Power-Down mode is entered immediately when
Table 203 on page 256
shows the effects of
Figure 89 on
PSD module
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