UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 147

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
24.6
16, 20, all the way up to 252. For example, if SPICLKD contains 24h, SPICLK has the
frequency of PERIH_CLK divided by 36 decimal.
The SPICLK frequency must be set low enough to allow the MCU time to read received data
bytes without loosing data. This is dependent upon many things, including the crystal
frequency of the MCU and the efficiency of the SPI firmware.
Dynamic control
At runtime, bits in registers SPICON0, SPICON1, and SPISTAT are managed by firmware
for dynamic control over the SPI interface. The bits Transmitter Enable (TE) and Receiver
Enable (RE) when set will allow transmitting and receiving respectively. If TE is disabled,
both transmitting and receiving are disabled because SPICLK is driven to constant output
logic ‘0’ (when SPO = 0) or logic '1' (when SPO = 1).
When the SSEL Bit is set, the SPISEL pin will drive to logic '0' (active) to select a connected
slave device at the appropriate time before the first data bit of a byte is transmitted, and
SPISEL will automatically return to logic '1' (inactive) after transmitting the eight bit of data,
as shown in
for each byte data transmission while the SSEL bit is set by firmware. When the SSEL Bit is
cleared, the SPISEL pin will drive to constant logic '1' and stay that way (after a transmission
in progress completes).
The Interrupt Enable Bits (TEIE, RORIE,TIE, and RIE) when set, will allow an SPI interrupt
to be generated to the MCU upon the occurrence of the condition enabled by these bits.
Firmware must read the four corresponding flags in the SPISTAT register to determine the
specific cause of interrupt. These flags are automatically cleared when firmware reads the
SPISTAT register.
Table 89.
Table 90.
Bit 7
Bit
–
7
6
5
4
Figure 46 on page
SPICON0: control register 0 (SFR D6h, reset value 00h)
SPICON0 register bit definition
Symbol
SPIEN
Bit 6
RE
TE
TE
–
Bit 5
R/W
RW
RW
RW
RE
–
145. SPISEL will continue to automatically toggle this way
Reserved
Transmitter Enable
0 = Transmitter is disabled
1 = Transmitter is enabled
Receiver Enable
0 = Receiver is disabled
1 = Receiver is enabled
SPI Enable
0 = Entire SPI Interface is disabled
1 = Entire SPI Interface is enabled
SPIEN
Bit 4
SSEL
Bit 3
SPI (synchronous peripheral interface)
Definition
FLSB
Bit 2
Bit 1
SBO
Bit 0
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