UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 91

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
19
19.1
Supervisory functions
Supervisory circuitry on the MCU module will issue an internal reset signal to the MCU
module and simultaneously to the PSD module as a result of any of the following four
events:
●
●
●
●
The resulting internal reset signal, MCU_RESET, will force the 8032 into a known reset state
while asserted, and then 8032 program execution will jump to the reset vector at program
address 0000h just after MCU_RESET is deasserted. The MCU module will also assert an
active low internal reset signal, RESET, to the PSD module. If needed, the signal RESET
can be driven out to external system components through any PLD output pin on the PSD
module. When driving this “RESET_OUT” signal from a PLD output, the user can choose to
make it either active-high or active-low logic, depending on the PLD equation.
External reset input pin, RESET_IN
The RESET_IN pin can be connected directly to a mechanical reset switch or other device
which pulls the signal to ground to invoke a reset.
RESET_IN is pulled up internally and enters a Schmitt trigger input buffer with a voltage
hysteresis of V
shown in
of t
t
long as the RESET_IN signal is active (it is not stretched). Refer to the Supervisor AC
specifications in
values.
Figure 22. Supervisor reset generation
RST_LO_IN
RST_FIL
The external RESET_IN pin is asserted
The low-voltage detect (LVD) circuitry has detected a voltage on V
threshold (power-on or voltage sags)
The JTAG debug interface has issued a reset command
The watchdog timer (WDT) has timed out
JTAG Debug
Figure
WDT
. The RESET_IN signal must be maintained at a logic '0' for at least a duration of
LVD
while the oscillator is running. The resulting MCU_RESET signal will last only as
RST_HYS
RESET_IN
22. RESET_IN is also filtered to reject a voltage spike less than a duration
Table 233 on page 286
PIN
for immunity to the effects of slow signal rise and fall times, as
V CC
t RST_ACTV
PULL-UP
DELAY,
at the end of this document for these parameter
S
R
Noise Filter
Q
Clock
MCU
Sync
Supervisory functions
CC
below a specific
MCU_RESET
to MCU and
Peripherals
RESET
to PSD Module
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