UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 295

• Manufacturer Part Number: UPSD3433E-40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4907

UPSD3422, UPSD3433, UPSD3434, UPSD3454
34.4
34.5
34.6
Workaround
Revision A and B - When a USB reset is detected, the USB SIE's registers must be
initialized appropriately by the firmware. The 3400 USB firmware examples clear USB SIE's
registers if USB reset is detected.
Data toggle
Description
The data toggle bit is read only.
Impact on application
The IN FIFO data toggle bit is controlled exclusively by the USB SIE; therefore, it is not
possible to change the state of the data toggle bit by firmware.
Workaround
Revision A - For cases where the data toggle bit must be reset, such as after a Clear
Feature/Stall request, sending the subsequent data on that endpoint twice results in getting
the data toggle bit back to the state that it should be.
Revision B - A change in silicon was made so that the data toggle bit is reset by disabling
and then enabling the respective endpoint's FIFO.
USB FIFO accessibility
Description
The USB FIFO is only accessible by firmware and not by a JTAG debugger.
Impact on application
Using a JTAG debugger, it is not possible to view the USB FIFO's contents in a memory
dump window.
Workaround
Revision A and B - None identified at this time.
Erroneous resend of data packet
Description
When a data packet is sent the respective IN FIFO busy bit is not automatically cleared by
the USB SIE. This can cause a data packet to be erroneously resent to the host in response
to an IN PID immediately after the first correct transmission of this data packet.
Impact on application
Since the Data Toggle in the retransmitted data packet is toggled from when the data was
first sent, the host will treat this packet as valid. If the identified workaround is not
Important notes
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