UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 174
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UPSD3433E-40U6
Manufacturer Part Number
UPSD3433E-40U6
Description
MCU 8BIT 8032 128KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3422EV-40U6.pdf
(300 pages)
Specifications of UPSD3433E-40U6
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4907
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPSD3433E-40U6
Manufacturer:
DENSO
Quantity:
83
Company:
Part Number:
UPSD3433E-40U6
Manufacturer:
STMicroelectronics
Quantity:
10 000
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USB interface
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Table 127. UCON register bit definition (continued)
●
Table 128. USB FIFO valid size (USIZE 0F2h, reset value 00h)
Table 129. USIZE register bit definition
Bit
0
Bit 7
6:0
Bit
USB FIFO valid size (USIZE)
The Endpoint selected by the USB endpoint select register (see
page
size (see
loaded into the IN FIFO that the SIE is to send in a Data packet for an Endpoint IN case
and indicates the number of bytes received for an Endpoint OUT case.
–
7
Symbol
172) determines the direction and FIFO that is controlled by the USB FIFO valid
BSY
Symbol
Table
SIZE
Bit 6
–
R/W
R/W
128). The USB FIFO valid size register indicates the number of bytes
Bit 5
FIFO Busy Status
– Endpoint IN Case
Once the FIFO has been loaded and armed (USIZE written with the
number of bytes to send), the BSY Bit is set and remains set until the
SIE has transmitted the data in the FIFO. The CPU should only access
the FIFO when BSY = 0.
– Endpoint OUT Case
While the SIE is receiving data and storing it in the FIFO (BSY = 1), it
should not be accessed by the CPU. Once the OUT transaction is
complete (BSY=0), the CPU may read the contents of the FIFO. The
BSY Bit will remain cleared until another OUT transaction is received.
R/W
R/W
–
Reserved
– Endpoint IN Case
The CPU writes the USIZE register with the number of bytes it
loaded into the IN endpoint FIFO for transmission with the next
IN transaction. Once the USIZE register has been written, the
FIFO becomes ready for transmission.
– Endpoint OUT Case
The CPU reads the USIZE register to determine how many
bytes were received in the data packet during the last OUT
transaction. This tells the CPU how many valid bytes to read
from the FIFO.
Note: Since the FIFOs are 64 bytes in length, the maximum
value for SIZE is 64 (40h).
Bit 4
UPSD3422, UPSD3433, UPSD3434, UPSD3454
SIZE[6:0]
Bit 3
Definition
Definition
Bit 2
Table 124 on
Bit 1
Bit 0
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