MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 130

• Manufacturer Part Number: MC908AZ32ACFU
• Description: IC MCU 32K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ32ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Low Voltage Inhibit (LVI)
14.3.1 Polled LVI Operation
In applications that can operate at V
polling the LVIOUT bit. In the configuration register, the LVIPWR bit must be at logic 1 to enable the LVI
module, and the LVIRST bit must be at logic 0 to disable LVI resets.
14.3.2 Forced Reset Operation
In applications that require V
module to reset the MCU when V
or more consecutive CPU cycles. In the configuration register, the LVIPWR and LVIRST bits must be at
logic 1 to enable the LVI module and to enable LVI resets.
14.3.3 False Reset Protection
The V
module to reset the MCU,V
CPU cycles. V
130
Addr.
$FE0F
DD
pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI
DETECTOR
Register Name
LOW V
DD
LVI Status Register
V
DD
must be above LVI
DD
V
V
(LVISR)
DD
DD
> LVI
< LVI
DD
DD
TRIP
CPU CLOCK
TRIP
must remain at or below the LVI
Figure 14-1. LVI Module Block Diagram
Figure 14-2. LVI I/O Register Summary
= 0
= 1
to remain above the LVI
ANLGTRIP
Read: LVIOUT
Write:
FROM CONFIG-1
DD
MC68HC908AZ32A Data Sheet, Rev. 2
LVIPWR
DD
falls to the LVI
TRIPR
Bit 7
levels below the LVI
DIGITAL FILTER
FROM CONFIG-1
Filter Bypass
for only one CPU cycle to bring the MCU out of reset.
Stop Mode
LVISTOP
V
DD
= Unimplemented
6
0
TRIPF
LVIOUT
TRIPF
level and remains at or below that level for nine
5
0
TRIPF
level, enabling LVI resets allows the LVI
TRIPF
FROM CONFIG-1
level, software can monitor V
4
0
LVIRST
level for nine or more consecutive
3
0
2
0
Freescale Semiconductor
LVI RESET
1
0
DD
Bit 0
by
0