HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 101
HPIXF1104BE.B1-994579
Manufacturer Part Number
HPIXF1104BE.B1-994579
Description
IC ETH MAC SPI3 4PORT 552-BGA
Manufacturer
Cortina Systems Inc
Specifications of HPIXF1104BE.B1-994579
Controller Type
Ethernet Controller, MAC
Interface
SPI-3
Voltage - Supply
1.2V, 2.5V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
575-BCBGA Exposed Pad (552 Bumps)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
1008-1020
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IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
5.6.2.3
5.6.2.4
5.6.2.5
Cortina Systems
Receiver Operational Overview
The receiver structure performs Clock and Data Recovery (CDR) on the incoming serial
data stream. The quality of this operation is a dominant factor for the Bit Error Rate (BER)
system performance. Feed forward and feedback controls are combined in one receiver
architecture for enhanced performance. The data is over-sampled and a digital circuit
detects the edge position in the data stream. A signal is not generated if an edge is not
found. A feedback loop takes care of low-frequency jitter phenomenon of unlimited
amplitude, while a feed forward section suppresses high-frequency jitter having limited
amplitude. The static edge position is held at a constant position in the over-sampled by a
constant adjustment of the sampling phases with the early and late signals.
Selective Power-Down
The IXF1104 MAC offers the ability to selectively power-down any of the SerDes TX or RX
ports that are not being used. This is done via
on page
Receiver Jitter Tolerance
The SerDes receiver architecture is designed to track frequency mismatch, recover phase,
and is tolerant of low-frequency data jitter.
sinusoidal jitter tracking capabilities.
®
IXF1104 4-Port Gigabit Ethernet Media Access Controller
209.
Figure 23
Table 149, TX and RX Power-Down ($0x787),
specifies the SerDes core receiver
Page 101
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