HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 112

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 31
5.8.4
Note:
Note:
Cortina Systems
Mode 0 Clock Cycle to Data Bit Relationship
When implemented on the board with the M5450 device, the LED DATA bit 1 appears on
Output bit 3 of the M5450 and the LED DATA bit 2 appears on Output bit 4, etc. This means
that Output bits 1, 2, and 15 through 35 will never have valid data and should not be used.
Mode 1: Detailed Operation
Please refer to generic specifications for 74LS/HC599 for information on device operation.
The operation of the LED Interface in Mode 1 is based on a 36-bit counter loop. The data for
each LED is placed in turn on the serial data line and clocked out by the LED_CLK.
30 on page 113
stream of each bit.
Figure 30 on page 113
is changed on the falling edge of the clock and is valid for the almost the entire clock cycle.
This ensures that the data is valid during the rising edge of the LED_CLK, which clocks the
data into the shift register chain devices.
The LED_LATCH signal is required in Mode 1, and latches the data shifted into the shift
register chain into the output latches of the 74HC599 device.
LED_LATCH signal is active High during the Low period on the 35th LED_CLK cycle. This
avoids any possibility of trying to latch data as it is shifting through the register.
When this operation mode is implemented on a board with a shift register chain containing
three 74HC599 devices, the LED DATA bit 1 is output on Shift register bit 1, and so on up
the chain. Only Shift register bits 31 and 32 do not contain valid data.
The actual data shown in
DATA. The 36-bit data chain is built up as shown in
The LED_DATA signal is now inverted from the state in Mode 0.
®
LED_CLK Cycle
IXF1104 4-Port Gigabit Ethernet Media Access Controller
36:38
4:15
2:3
1
shows the basic timing relationship and relative positioning in the data
START BIT
PAD BITS
LED DATA 1-12
PAD BITS
LED_DATA
Name
shows the 36 clocks which are output on the LED_CLK pin. The data
Figure 30
LED_DATA Description
This bit synchronizes the M5450 device to expect 35 bits of data to
follow.
These bits are used only as fillers in the data stream to extend the
length from the actual 12-bit LED DATA to the required 18-bit frame
length. These bits should always be a logic 0.
These bits are the actual data transmitted to the M5450 device. The
decode for each individual bit in each mode is defined in
page
The data is TRUE. Logic 1 (LED ON) = High
These bits are used as fillers in the data stream to extend the length
from the actual 30-bit LED DATA to the required 36-bit frame length.
These bits should always be a logic 0.
consists of a 36-bit chain, of which 12 bits are valid LED
113.
Figure
30.
Figure 30
shows that the
Table 33 on
Page 112
Figure