HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 9

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HPIXF1104BE.B1-994579

Manufacturer Part Number
HPIXF1104BE.B1-994579
Description
IC ETH MAC SPI3 4PORT 552-BGA
Manufacturer
Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

Controller Type
Ethernet Controller, MAC
Interface
SPI-3
Voltage - Supply
1.2V, 2.5V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
575-BCBGA Exposed Pad (552 Bumps)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
1008-1020

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Manufacturer
Quantity
Price
Part Number:
HPIXF1104BE.B1-994579
Manufacturer:
Cortina Systems Inc
Quantity:
135
Part Number:
HPIXF1104BE.B1-994579
Manufacturer:
National
Quantity:
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Part Number:
HPIXF1104BE.B1-994579
Manufacturer:
Cortina Systems Inc
Quantity:
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IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Cortina Systems
Page #
193
195
196
198
199
201
207
208
209
210
211
212
213
215
221
222
222
222
NA
NA
NA
180(old)
Page #
19
53
60
®
Description
Modified
($0x581)”,
Port 3 ($0x583)”
Renamed and modified
[old register name: RX FIFO Number of Frames Removed Ports 0 to 3; renamed bit names to match register
names; removed “This register gets updated after one cycle of sw reset is applied” under Description].
Modified
name].
Renamed/modified
page 198
register name].
Modified
changed description and type for bits 7:0].
Renamed
Size; changed bit names and edited/added text under description].
Modified
and bit name].
Modified
FIFO Number of Frames Removed Ports 3 - 0].
Modified
FIFO Number of Dropped Packets Ports 0-3 and text under the description].
Modified
Modified
bits 9:8; changed default for bits 4:0].
Modified
Modified
changed description text].
Modified
and MPHY modes].
Modified
of the Register Description; renamed bits to match caption; changed text under Description].
Added note under
Modified
Modified
Removed/Reserved Table 190 “TX and RX AC/DC Coupling Selection ($7x780)”.
Deleted old Figure 19, “Typical GBIC Module Functional Diagram” under
Interface”.
Removed old Section 5.1.1.5, “Pause Command Frames.”
Removed old Table 13. TX FIFO Mini Frame Size for MAC and Padding Enable Port 0 to 3 Register (Addr:
0x63E) and replaced with Reserved.
Description
Modified
Modified
Modified text for etherStatsCollision in
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 152 “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)”
Table 113 “RX FIFO High Watermark Port 0
Table 123 “RX FIFO Errored Frame Drop Enable ($0x59F)”
Table 126 “RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)”
Table 136 “Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)”
Table 138 “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)”
Table 139 “TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)”
Table 141 “TX FIFO Port Drop Enable ($0x63D)”
Table 142 “MDIO Single Command ($0x680)”
Table 144 “Autoscan PHY Address Enable ($0x682)”
Table 146 “SPI3 Transmit and Global Configuration ($0x700)”
Table 147 “SPI3 Receive Configuration ($0x701)”
Table 153 “Optical Module Status Ports 0-3 ($0x799)”
Table 154 “Optical Module Control Ports 0 - 3 ($0x79A)”
Table 1 “IXF1104 Signal Descriptions”
Section 5.1.1.1, “Padding of Undersized Frames on
[older register name: RX FIFO Dropped Packet Counter for Ports 0 to 3; renamed bit names to match
Table 128 “RX FIFO Transfer Threshold Port 0 ($0x5B8)” on page 201
Table 115 “RX FIFO High Watermark Port 2
[changed bits 11:0 description].
Section 8.4.11, “Optical Module Register
Table 125 “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5)” on
Table 121 “RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 – 0x597)”
Revision Date: August 21, 2003
Revision Date: March 24, 2004
Revision Number: 007
Revision Number: 006
(Sheet 5 of 5)
(Sheet 1 of 2)
Table 9 “RMON Additional
($0x580)”,
($0x582)”, and
[changed default; changed description and default for
[changed description for bits 3:0].
[broke out bits and modified all text adding SPHY
Overview”.
Transmit”.
[added note to register description].
[edited register description].
Table 114 “RX FIFO High Watermark Port 1
Statistics”.
[changed register description].
[renamed bit names to match register
Table 116 “RX FIFO High Watermark
[broke out bits 19:16, 7:4, and 3:0 and
Section 5.7, “Optical Module
[renamed heading and bit name;
[from “RX FIFO Jumbo Packet
[deleted second paragraph
[renamed from TX
[renamed heading
[renamed from TX
Page 9

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