HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 192

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 127
Table 128
Table 129
Cortina Systems
RX FIFO Transfer Threshold Port 0 ($0x5B8) (Sheet 2 of 2)
RX FIFO Transfer Threshold Port 1 ($0x5B9)
RX FIFO Transfer Threshold Port 2 ($0x5BA)
®
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
Register Description: RX FIFO transfer threshold for port 1in 8-byte location.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
Register Description: RX FIFO transfer threshold for port 2 in 8-byte location.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
31:12
31:12
31:12
11:0
11:0
11:0
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Bit
Bit
clear; R/W/C = Read/Write, Clear on Write
clear; R/W/C = Read/Write, Clear on Write
clear; R/W/C = Read/Write, Clear on Write
Reserved
RX FIFO Transfer
Threshold - Port 0
Name
Reserved
RX FIFO Transfer
Threshold - Port 1
Name
Reserved
RX FIFO Transfer
Threshold - Port 2
Reserved
RX FIFO transfer threshold for port 0. This must
be less than the RX FIFO High water mark.
User definable control register that sets the
threshold where a packet starts transitioning to the
SPI3 interface from the RX FIFO before the EOP
is received. Packets received in the RX FIFO
below this threshold are treated as store and
forward.
Note:
Description
Reserved
RX FIFO transfer threshold for port 1. This must
be less than the RX FIFO High watermark.
User definable control register that sets the
threshold where a packet starts transitioning to
the SPI3 interface from the RX FIFO before the
EOP is received. Packets received in the RX
FIFO below this threshold are treated as store
and forward.
Note:
Description
Reserved
RX FIFO transfer threshold for port 2. This must be
less than the RX FIFO High water mark.
User definable control register that sets the
threshold where a packet starts transitioning to the
SPI3 interface from the RX FIFO before the EOP is
received. Packets received in the RX FIFO below
this threshold are treated as store and forward.
Note:
Do not program the RX FIFO transfer
threshold below a setting of 0xBE
(1520bytes).
Do not program the RX FIFO transfer
threshold below a setting of 0xBE
(1520bytes).
Do not program the RX FIFO transfer
threshold below a setting of 0xBE
(1520bytes).
Type
Type
R/W
R/W
R/W
RO
RO
RO
0x000000BE
0x000000BE
0x00000
0x00000
Default
0x00000
Default
0x0BE
0x0BE
0x0BE
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