HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 208

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 146
Table 147
8.4.10
Table 148
Cortina Systems
SPI3 Receive Configuration ($0x701) (Continued) (Sheet 4 of 4)
Address Parity Error Packet Drop Counter ($0x70A)
SerDes Register Overview
Table 148
($0x794), on page 210
which contain the control and status for the four SerDes interfaces on the IXF1104 MAC.
TX Driver Power Level Ports 0 - 3 ($0x784) (Sheet 1 of 2)
®
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
Register Description: This register counts the number of packets dropped due to parity error
detection during the address selection cycle.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
Register Description: Allows selection of various programmable drive strengths on each
SerDes port. Refer to
page
31:8
Bit
6:1
Bit
7:0
31:16
IXF1104 4-Port Gigabit Ethernet Media Access Controller
7
0
Bit
clear; R/W/C = Read/Write, Clear on Write
clear; R/W/C = Read/Write, Clear on Write
100.
Name
Rx_core_enable
IBA[5:0]
RERR_enable
Name
Reserved
Address Parity Error
Packet Drop Counter
Name
Reserved
through
Section 5.6.2.2, Transmitter Programmable Driver-Power Levels, on
Table 151, Clock and Interface Mode Change Enable Ports 0 - 3
define the contents of the SerDes registers at base location 0x780,
Reserved
This is an 8-bit counter that counts the number of
packets dropped due to parity error detection
during the address selection cycle. This gets
cleared when read and saturates at 8’hFF. There
is only one counter for address parity drop as
address will be used only in MPHY mode of
operation. The counter gets cleared once the
register is read.
Description
Description
Reserved
Description
SPHY Mode:
NA. Write as 1, ignore on Read.
MPHY Mode:
0 = Disables the RX SPI3 core.
1 = Enables the RX SPI3 core.
SPHY Mode:
NA. Write as 0, ignore on Read.
MPHY Mode:
Sets the 6-bit value appended to the 2-bit
address during the port address selection.
SPHY Mode/MPHY Mode:
Frames marked to be filtered (based on the
settings in
($0x59F)
RERR when sent out the SPI3 interface.
0 = Packets not indicated with RERR.
1 = Packets indicated with RERR.
can be optionally indicated with an
RX FIFO Errored Frame Drop Enable
Type
Type
Type
RO
R/W
R/W
R/W
RO
R
1
1
0x00000000
0x0000dddd
0x000000
Default
Default
Default
0x0000
0x00
0x00
0x1
0
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