HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 165

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 90
Table 91
8.4.2
Cortina Systems
RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 2 of 2)
Port Multicast Address ($ Port_Index +0x1A – +0x1B)
MAC RX Statistics Register Overview
The MAC RX Statistics registers contain the MAC receiver statistic counters and are cleared
when read. The software polls these registers and accumulates values to ensure that the
counters do not wrap. The 32-bit counters wrap after approximately 30 seconds.
Table 92
1, 2, or 3).
®
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
2. Used in conjunction with the
Name
Port Multicast
Address Low
Port Multicast
Address High
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
Bit
IXF1104 4-Port Gigabit Ethernet Media Access Controller
2
1
0
clear; R/W/C = Read/Write, Clear on Write
allows the frame to be dropped in the RX FIFO. Otherwise, the frame is sent out the SP3 interface and
may be optionally signaled with an RERR (see bit 0 of
FIFO Errored Frame Drop Enable
clear; R/W/C = Read/Write, Clear on Write
Name
B/Cast Drop En
M/Cast Match En
U/Cast Match En
covers the RX statistics for the four MAC ports. Port_Index is the port number (0,
Description
This address compares against multicast frames
at the receiving side if multicast filtering is
enabled.
This register contains bits 31:0 of the address.
This address compares against multicast frames
at the receiving side if Multicast filtering is
enabled.
This register contains bits 47:32 of the address.
2
Table 122, RX FIFO Errored Frame Drop Enable ($0x59F), on page
Description
This bit enables a Global filter on broadcast
frames.
0 = All broadcast frames are passed to the SPI3
1 = All broadcast frames are dropped.
This bit enables a filter on multicast frames.
0 = All muticast frames are good and passed to
1 = Only multicast frames with a destination
This bit enables a filter on unicast frames.
0 = All unicast frames are good and are passed to
1 = Only unicast frames with a Destination
Note:
Interface.
the SPI3 Interface.
address that matches the
PortMulticastAddress are forwarded. All other
muticast frames are dropped.
the SPI3 Interface.
Address that matches the Station Address are
forwarded. All other unicast frames are
dropped.
($0x59F).
The VLAN filter overrides the unicast filter.
Therefore, a VLAN frame cannot be
filtered based on the unicast address.
2
RX FIFO Errored Frame Drop Enable ($0x59F)RX
2
2
Port_Index
Port_Index
Address
+ 0x1A
+ 0x1B
Type
Type
R/W
R/W
R/W
R/W
R/W
1
*
0x00000000
0x0000000
Default
Default
188. This
0
0
0
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