HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 36

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
4.0
4.1
4.1.1
4.1.2
4.2
Cortina Systems
Ball Assignments and Signal Descriptions
Naming Conventions
Signal Name Conventions
Signal names begin with a Signal Mnemonic, and can also contain one or more of the
following designations: a differential pair designation, a serial designation, a port
designation (RGMII interface), and an active low designation. Signal naming conventions
are as follows:
Differential Pair + Port Designation. The positive and negative components of differential
pairs tied to a specific port are designated by the Signal Mnemonic, immediately followed by
an underscore and either P (positive component) or N (negative component), and an
underscore followed by the port designation. For example, SerDes interface signals for port
0 are identified as TX_P_0 and TX_N_0.
Serial Designation. A set of signals that are not tied to any specific port are designated by
the Signal Mnemonic, followed by a bracketed serial designation. For example, the set of 11
CPU Address Bus signals is identified as UPX_ADD[10:0].
Port Designation. Individual signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by an underscore and the Port Designation. For
example, RGMII Transmit Control signals are identified as TX_CTL_0, TX_CTL_1,
TX_CTL_2, and so on.
Port Bus Designation. A set of bus signals that apply to a particular port are designated by
the Signal Mnemonic, immediately followed by a bracketed bus designation, followed by an
underscore and the port designation. For example, RGMII transmit data bus signals are
identified as TD[3:0]_0, TD[3:0]_1, TD[3:0]_2, and so on.
Active Low Designation. A control input or indicator output that is active Low is designated
by a final suffix consisting of an underscore followed by an upper case “L”. For example, the
CPU cycle complete identifier is shown as UPX_RDY_L.
Register Address Conventions
Registers located in on-chip memory are accessed using a register address, which is
provided in Hex notation. A Register Address is indicated by the dollar sign ($), followed by
the memory location in Hex.
Interface Signal Groups
This section describes the IXF1104 MAC signals in groups according to the associated
interface or function.
®
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Figure 4
shows the various interfaces available on the IXF1104 MAC.
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