HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 76

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
5.1.6.3
5.1.7
5.1.7.1
5.1.7.1.1
5.1.7.1.2
Cortina Systems
The IXF1104 MAC checks the CRC for all legal-length jumbo frames (frames between 1519
and the Max Frame Size). On transmission, the MAC can be programmed to append the
CRC to the frame or check the CRC and increment the appropriate counter. On reception,
the MAC transmits these frames across the SPI3 interface (jumbo frames above the setting
in the
are sent across the SPI3 interface). If the receive frame has a bad CRC, the appropriate
counter increments and the RxERR flag is asserted on the SPI3 receive interface.
Jumbo frames also impact flow control. The maximum frame size needs to be taken into
account when determining the FIFO watermarks. The current transmission must be
completed before a Pause frame is transmitted (needed when the receiver FIFO High
watermark is exceeded). If the current transmission is a jumbo frame, the delay may be
significant and increase data loss due to insufficient available FIFO space.
Loss-less Flow Control
The IXF1104 MAC supports loss-less flow control when the size of a Jumbo packet is
restricted to 9.6 k bytes. If this condition is met, the IXF1104 MAC has sufficient memory
resources allocated to each MAC port to ensure that, if both the IXF1104 MAC and link
partner are required to send Pause packets simultaneously during jumbo packet transfers
across a medium of five kilometers of fiber, no packet data should be lost due to FIFO
overflows.
Packet Buffer Dimensions
TX and RX FIFO Operation
TX FIFO
The IXF1104 MAC TX FIFOs are implemented with 10 KB for each channel. This provides
enough space for at least one maximum size (10 KB) packet per-port storage and ensures
that no under-run conditions occur, assuming that the sending device can supply data at the
required data rate.
A transfer to MAC Threshold parameter, which is user-programmable, determines when the
FIFO signals to the MAC that it has data to send. This is configured for specific block sizes,
and the user must ensure that an under-run does not occur. Also, the threshold can be set
above the maximum size of a normal Ethernet packet. This causes the FIFO to send only
data to the MAC when this threshold is exceeded or when the End-of-Packet marker is
received. This second condition eliminates the possibility of under-run, except when the
controlling switch device fails. It can, however, cause idle times on the media.
RX FIFO
The IXF1104 MAC RX FIFOs are provisioned so that each port has its own 32 KB of
memory space. This is enough memory to ensure that there is never an over-run on any
channel while transferring normal Ethernet frame size data.
The FIFOs automatically generate Pause control frames to halt the link partner when the
High watermark is reached and to restart the link partner when the data stored in the FIFO
falls below the low-watermark. The RX and TX FIFOs have been sized to support lossless
flow control with 9.6 KB packets. The RX FIFO has a programmable transfer threshold that
sets the threshold at which packets become “cut through” and starts transitioning to the
®
• TxExcessiveLengthDrop (Addr: Port_Index + 0x53)
• TxCRCError (Addr: Port_Index + 0x56)
IXF1104 4-Port Gigabit Ethernet Media Access Controller
RX FIFO Transfer Threshold Port 0 ($0x5B8)
with a bad CRC cannot be dropped and
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