HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 8

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Cortina Systems
Page #
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®
Description
Modified
Modified second paragraph under
Modified
Added note under
Modified
Changed
Changed
Added new
Modified
AVDD2P5_2; changed “PLL1_VDDA and PLL2_VDDA to AVDD1P8_1; changed PLL3_VDDA to AVDD2P5_1.
Modified
AVDD2P5_2; changed “PLL1_VDDA and PLL2_VDDA to AVDD1P8_1; changed PLL3_VDDA to AVDD2P5_1.
Modified
Modified
Modified
Replaced old MDIO Timing diagram and table with
Read Timing
Broke up the old Register Map into
RX Statistics Registers ($ Port Index +
Table 62 “PHY Autoscan Registers ($ Port Index +
($ 0x500 -
0x63E)”,
“SerDes Registers ($ 0x780 -
Edited
Edited
Edited
Edited
Edited
Edited
Edited
Modified
description.
Modified
Modified
description and type for bits 13:12].
Modified
Modified
changed bits 3:1 to Reserved; added table note 2].
Renamed/modified
heading; added table note 2].
Modified
RxPauseMacControlReceivedCounter description; edited note 3 and added note 4].
Modified
frame size” for Txpkts1519toMaxOctets description].
Modified
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 63 “Global Status and Configuration Registers ($ 0x500 - 0X50C)”
Table 64 “RX FIFO Registers ($ 0x580 - 0x5BF)”
Table 65 “TX FIFO Registers ($ 0x600 - 0x63E)”
Table 66 “MDIO Registers ($ 0x680 - 0x683)”
Table 67 “SPI3 Registers ($ 0x700 - 0x716)”
Table 68 “SerDes Registers ($ 0x780 - 0x798)”
Table 69 “Optical Module Registers ($ 0x799 - 0x79F)”
Table 37 “Byte Swapper Behavior”
Figure 33 “SPI3 Interface Loopback
Figure 34 “Line Side Interface Loopback
Table 39 “Absolute Maximum Ratings”
Table 40 “Recommended Operating Conditions”
Table 42 “SerDes Transmit Characteristics”
Table 49 “GMII 1000BASE-T Transmit Signal Parameters”
Table 50 “GMII 1000BASE-T Receive Signal Parameters”
Table 66 “MDIO Registers ($ 0x680 -
Table 71 “Desired Duplex ($ Port_Index + 0x02)”
Table 84 “FC Enable ($ Port_Index + 0x12)”
Table 88 “RX Config Word ($ Port_Index + 0x16)”
Table 89 “TX Config Word ($ Port_Index + 0x17)”
Table 90 “Diverse Config Write ($ Port_Index + 0x18)”
Table 93 “MAC RX Statistics ($ Port_Index + 0x20 – + 0x39)”
Table 94 “MAC TX Statistics ($ Port_Index +0x40 – +0x58)”
Section 5.12, “Clocks”
Section 5.12.6, “I2C Clock”
Table 82 “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)”
0X50C)”,
Section 6.0,
Diagram”, and
Section 5.11.2, “Line Side Interface
Table 91 “RX Packet Filter Control ($ Port_Index + 0x19)”
Table 64 “RX FIFO Registers ($ 0x580 -
“Applications”.
Table 52 “MDIO Timing
Revision Date: March 24, 2004
0x798)”, and
[from GBIC output clock to I
Revision Number: 007
Section 5.10, “TAP Interface (JTAG)”
Table 59 “MAC Control Registers ($ Port Index +
[from GBIC Clock to I
(Sheet 4 of 5)
Offset)”,
Table 69 “Optical Module Registers ($ 0x799 -
[edited/added new values].
Path”.
0x683)”,
Table 61 “MAC TX Statistics Registers ($ Port Index +
[changed SerDes analog power to AVDD1P8_2 and
Path”.
Offset)”,
Figure 43 “MDIO Write Timing
[no offset].
Parameters”.
[no offset].
[included SerDes power driver level information].
[changed description for bits 1:0].
Loopback”.
[no offset].
Table 67 “SPI3 Registers ($ 0x700 -
[no offset].
[no offset].
[changed SerDes analog power to AVDD1P8_2 and
[changed 100 Mbps to 1000 Mbps in register
2
Table 63 “Global Status and Configuration Registers
[edited description and type for bits 14, 13:12.
[edited Register Description text; changed
C Clock].
2
0x5BF)”,
C Clock].
[no offset].
[edited description and type for bits 18:8;
(changed Min values for t1 and t2.
(changed Min values for t1 and t2.
[changed “1526-max” to “1523 - max
Table 65 “TX FIFO Registers ($ 0x600 -
[added note to
[Added text to register description.]
[old register name - added RX to
[no offset].
Diagram”,
Offset)”,
0x79F)”.
0x716)”,
Figure 44 “MDIO
Table 60 “MAC
Table 68
Offset)”,
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