HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 81

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Note:
5.2.1.2
5.2.2
5.2.2.1
Cortina Systems
In the receive direction, the IXF1104 MAC specifies the selected port by sending the
address on the RDAT[1:0] bus marked with the RSX signal active and RVAL signal inactive.
All subsequent RDAT[1:0] bus operations marked with RSX inactive and RVAL active are
packet data from the specified port.
See
mode signals. The control signals with the port designator for Port 0 are the only ones used
in MPHY mode and they apply to all 4 ports.
page 38
SPI3 RX Round Robin Data Transmission
The IXF1104 MAC uses a round-robin protocol to service each of the 4 ports dependent
upon the enable status of the port and if there is data available to be taken from the RX
FIFO. The round robin order goes from port 0, port 1, port 2, port 3, and back to port 0. A
port is skipped and the next port is serviced if it has no available transmit data. The data
transfer bursts are user-configurable burst lengths of 64, 128, or 256 bytes. The IXF1104
MAC also has a configurable pause interval between data transfer bursts on the receive
side of the interface. The RX SPI3 burst lengths and the pause interval can be set in the
SPI3 Receive Configuration
MPHY Logical Timing
The SPI3 interface AC timing for MPHY can be found in
Specifications, on page
associated with MPHY mode.
Transmit Timing
In MPHY mode a packet transmission starts with the TSX signal indicating port address
information is on the data bus. The next clock cycle TENB and TSOP indicate present data
on the bus is the first word in the packet and all subsequent clocks will contain valid data as
long as TENB is active or until TEOP is asserted. Data transmission can be temporally
halted when TENB goes high then resumed when TENB is low. The valid bytes in the final
word, during an active TEOP, are indicated by state of TMOD [1:0].
®
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 16, SPI3 MPHY/SPHY Interface, on page 58
provides a comprehensive list of SPI3 signal descriptions.
130. Logical timing in the following diagrams illustrates all signals
($0x701)).
Table 3, SPI3 Interface Signal Descriptions, on
for a complete list of the MPHY
Section 7.2, SPI3 AC Timing
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