HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 187

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 119
Table 120
Table 121
Cortina Systems
RX FIFO Low Watermark Port 3 ($0x58D)
RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 – 0x597)
RX FIFO Port Reset ($0x59E) (Sheet 1 of 2)
®
Register Description: The default value of 0x072 represents 114 eight-byte locations. This
equates to 912 bytes of data. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO falls below the Low watermark, flow control is
automatically de-asserted within the MAC to allow more line-side data to be captured by the
RX FIFO.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
Name
RX FIFO Overflow
Frame Drop
Counter on port 0
RX FIFO Overflow
Frame Drop
Counter on port 1
RX FIFO Overflow
Frame Drop
Counter on port 2
RX FIFO Overflow
Frame Drop
Counter on port 3
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
Register Description: The soft reset register for each port in the RX block. Port ID = bit
position in the register. To make the reset active, the bit must be set High. For example, reset
of port 1 implies register value = 0000_0018. Setting the bit to 0 de-asserts the reset.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
31:12
11: 0
31:4
Bit
Bit
IXF1104 4-Port Gigabit Ethernet Media Access Controller
3
clear; R/W/C = Read/Write, Clear on Write
clear; R/W/C = Read/Write, Clear on Write
clear; R/W/C = Read/Write, Clear on Write
Name
Reserved
RX FIFO Low
Watermark Port 3
Name
Reserved
Reset RX FIFO for
Port 3
Description
When RX FIFO on port 0 becomes full or
reset, the number of frames lost/dropped on
this port are shown in this register.
When RX FIFO on port 1 becomes full or
reset, the number of frames lost/dropped on
this port are shown in this register.
When RX FIFO on port 2 becomes full or
reset, the number of frames lost/dropped on
this port are shown in this register.
When RX FIFO on port 3 becomes full or
reset, the number of frames lost/dropped on
this port are shown in this register.
Reserved
Reserved
Description
The High watermark value
Note:
Description
Port 3
0 = De-assert reset
1 = Reset
Should never be greater or equal to the
High Watermark.
Address
0x594
0x595
0x596
0x597
Type
Type
Type
R/W
R/W
R
R
R
R
RO
RO
1
1
1
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x0000000
0x00000
Default
Default
Default
0x072
0x072
0
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