HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 42

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 3
Cortina Systems
SPI3 Interface Signal Descriptions (Sheet 5 of 8)
®
MPHY
RDAT31
RDAT30
RDAT29
RDAT28
RDAT27
RDAT26
RDAT25
RDAT24
RDAT23
RDAT22
RDAT21
RDAT20
RDAT19
RDAT18
RDAT17
RDAT16
RDAT15
RDAT14
RDAT13
RDAT12
RDAT11
RDAT10
RDAT9
RDAT8
RDAT7
RDAT6
RDAT5
RDAT4
RDAT3
RDAT2
RDAT1
RDAT0
RFCLK
RPRTY_0
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Signal Name
SPHY
RDAT7_3
RDAT6_3
RDAT5_3
RDAT4_3
RDAT3_3
RDAT2_3
RDAT1_3
RDAT0_3
RDAT7_2
RDAT6_2
RDAT5_2
RDAT4_2
RDAT3_2
RDAT2_2
RDAT1_2
RDAT0_2
RDAT7_1
RDAT6_1
RDAT5_1
RDAT4_1
RDAT3_1
RDAT2_1
RDAT1_1
RDAT0_1
RDAT7_0
RDAT6_0
RDAT5_0
RDAT4_0
RDAT3_0
RDAT2_0
RDAT1_0
RDAT0_0
RFCLK
RPRTY_0
RPRTY_1
RPRTY_2
RPRTY_3
Designator
Ball
G24
G23
G22
G21
G20
G19
G18
D22
C22
C21
C20
D16
C17
D14
C13
C14
G16
F24
E21
E22
B22
B20
F18
E18
E17
F16
E16
A17
F14
E14
B14
A14
A15
A19
E15
E20
F20
Output
Output
Output
Output
Output
Type
Input
Standard
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Description
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Receive Clock.
RFCLK is the clock associated with all
receive signals. Data and controls are
driven on the rising edge of RFCLK
(frequency operation range 90 - 133 MHz).
Receive Parity.
RPRTY indicates odd parity for the RDAT
bus. RPRTY is valid only when a channel
asserts RENB or RSX. Odd parity is the
default configuration; however, even parity
can be selected (see
page
32-bit Multi-PHY mode: RPRTY_0 is the
parity bit for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
RPRTY_0:3 corresponds to the respective
RDAT[3:0]_n channel.
205).
Table 146 on
Bits
[31:24]
[7:0] for port 3
Bits
[23:16]
[7:0] for port 2
Bits
[15:8]
[7:0] for port 1
Bits
[7:0]
[7:0] for port 0
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