A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 103
Manufacturer Part Number
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
Specifications of A3PN125-ZVQG100
Number Of Macrocells
Maximum Operating Frequency
Number Of Programmable I/os
Data Ram Size
Supply Voltage (max)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Supply Voltage (min)
Number Of Gates
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Revision 1 (cont’d)
DC and Switching
table note 4: "For nano devices, the VQ100 package is offered in both leaded and
RoHS-compliant versions. All other packages are RoHS-compliant only."
updated to remove QN100 for A3PN250.
number of gates and dual-port RAM for ProASIC3 nano devices.
The device architecture figures,
Overview with Two I/O Banks (A3PN060 and A3PN125)
ProASIC3 nano Device Architecture Overview with Four I/O Banks
Banks and No RAM (A3PN010 and A3PN030)
A3PN020 and smaller devices.
Table 2-2 • Recommended Operating Conditions
the VCCI row. The following table note was added: "VMV pins must be connected
to the corresponding VCCI pins."
The values in
for A3PN010, A3PN015, and A3PN020.
A table note, "All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide
range, as specified in the JESD8-B specification," was added to
Summary of Maximum and Minimum DC Input and Output
Summary of I/O Timing Characteristics—Software Default Settings (at 35
Settings (at 10
3.3 V LVCMOS Wide Range was added to
Note 2 for the
was added/changed to "The die attach paddle of the package is tied to ground
left corner instead of the upper right corner.
"PLL and CCC" section
"General Description" section
"I/Os Per Package"
"ProASIC3 nano Product Available in the Z Feature Grade" section
Table 2-19 • Summary of I/O Timing Characteristics—Software Default
Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O
Table 2-7 • Quiescent Supply Current Characteristics
pin diagram was revised.
pin diagram was revised to move the pin IDs to the upper
table was updated to add the following information to
was revised to include information about CCC-GLs in
Table 2-23 • I/O Short Currents I
Figure 1-3 • ProASIC3 nano Device Architecture
R e v i s i o n 8
was updated to give correct information about
Table 2-21 • I/O Output Buffer
was revised to add VMV to
ProASIC3 nano Flash FPGAs
Figure 1-4 •
Table 2-14 •
Table 2-18 •