A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 22

FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part Number
A3PN125-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN125-ZVQG100

Processor Series
A3PN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Delay Time
1.02 ns
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ProASIC3 nano DC and Switching Characteristics
Table 2-10 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 nano Devices
Table 2-11 • Different Components Contributing to the Static Power Consumption in ProASIC3 nano Devices
2 - 8
Parameter
P
P
P
P
P
P
P
P
P
P
P
P
P
Note:
Parameter
P
P
P
Notes:
1. Minimum contribution of the PLL when running at lowest frequency.
2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet calculator
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
DC1
DC4
DC5
or SmartPower tool in Libero IDE.
For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet
calculator or SmartPower tool in Libero
Power Consumption of Various Internal Resources
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
Clock contribution of a VersaTile used as a
sequential module
First contribution of a VersaTile used as a
sequential module
Second contribution of a VersaTile used as a
sequential module
Contribution of a VersaTile used as a
combinatorial Module
Average contribution of a routing net
Contribution of an I/O input pin
(standard-dependent)
Contribution of an I/O output pin
(standard-dependent)
Average contribution of a RAM block during a read
operation
Average contribution of a RAM block during a write
operation
Dynamic contribution for PLL
Array static power in Active mode
Static PLL contribution
Bank quiescent power (VCCI-dependent)
Definition
1
Definition
®
Integrated Design Environment (IDE) software.
R e vi s i o n 8
11.03
1.58
Device Specific Dynamic Contributions
25.00
30.00
11.03
2.60
Device Specific Static Power (mW)
0.81
See
See
See
See
Table 2-8 on page
Table 2-9 on page
2.55
0.81
(µW/MHz)
Table 2-7 on page
Table 2-7 on page
9.3
0.81
0.12
0.07
0.29
0.29
0.70
9.3
0.4
2-6.
2-7.
N/A
N/A
N/A
9.3
0.4
N/A
2-6.
2-6.
9.3
0.4

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