A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 78

FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part Number
A3PN125-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN125-ZVQG100

Processor Series
A3PN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Delay Time
1.02 ns
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3PN125-ZVQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3PN125-ZVQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
ProASIC3 nano DC and Switching Characteristics
Table 2-75 • RAM512X18
2- 64
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
AS
AH
ENS
ENH
DS
DH
CKQ1
CKQ2
C2CRWH
C2CWRH
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
derating values.
Commercial-Case Conditions: T
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock HIGH to new data valid on DO (output retained, WMODE = 0)
Clock HIGH to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable read access after write on same
address; applicable to opening edge
Address collision clk-to-clk delay for reliable write access after read on same
address; applicable to opening edge
RESET_B LOW to data out LOW on DO (flow-through)
RESET_B LOW to data out LOW on DO (pipelined)
RESET_B removal
RESET_B recovery
RESET_B minimum pulse width
Clock cycle time
Maximum frequency
J
Description
= 70°C, Worst-Case VCC = 1.425 V
R e visio n 8
Table 2-6 on page 2-5
0.25 0.28 0.33
0.00 0.00 0.00
0.09 0.10 0.12
0.06 0.07 0.08
0.18 0.21 0.25
0.00 0.00 0.00
2.16 2.46 2.89
0.90 1.02 1.20
0.50 0.43 0.38
0.59 0.50 0.44
0.92 1.05 1.23
0.92 1.05 1.23
0.29 0.33 0.38
1.50 1.71 2.01
0.21 0.24 0.29
3.23 3.68 4.32
310
–2
272
–1
for
Std. Units
231 MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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