A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 12

FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano


Manufacturer Part Number
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

Specifications of A3PN125-ZVQG100

Processor Series
IP Core
Number Of Macrocells
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
Data Ram Size
36 Kbit
Delay Time
1.02 ns
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ProASIC3 nano Device Overview
1 - 6
programming file support is also included to allow for easy programming of large numbers of parts with
differing FlashROM contents.
ProASIC3 nano devices (except the A3PN030 and smaller devices) have embedded SRAM blocks along
their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available
memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have
independent read and write ports that can be configured with different bit widths on each port. For
example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM
blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro
(except in A3PN030 and smaller devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
Higher density ProASIC3 nano devices using either the two I/O bank or four I/O bank architectures
provide the designer with very flexible clock conditioning capabilities. A3PN060, A3PN125, and
A3PN250 contain six CCCs. One CCC (center west side) has a PLL. The A3PN030 and smaller devices
use different CCCs in their architecture. These CCC-GLs contain a global MUX but do not have any
PLLs or programmable delays.
For devices using the six CCC block architecture, these six CCC blocks are located at the four corners
and the centers of the east and west sides.
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay
operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the
FPGA core or from dedicated connections to the CCC block, which are located near the CCC.
The CCC block has these key features:
Additional CCC specifications:
Global Clocking
ProASIC3 nano devices have extensive support for multiple clocking domains. In addition to the CCC
and PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high fanout nets.
Wide input frequency range (f
Output frequency range (f
Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
Maximum acquisition time = 300 µs (for PLL only)
Low power consumption of 5 mW
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /
) (for PLL only)
) = 0.75 MHz to 350 MHz
) = 1.5 MHz to 350 MHz
R e vi s i o n 8

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