A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 36

FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part Number
A3PN125-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN125-ZVQG100

Processor Series
A3PN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Delay Time
1.02 ns
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ProASIC3 nano DC and Switching Characteristics
Table 2-27 • Minimum and Maximum DC Input and Output Levels
Figure 2-6 • AC Loading
Table 2-28 • 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
2- 22
3.3 V LVTTL /
3.3 V LVCMOS
Drive Strength
2 mA
4 mA
6 mA
8 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input LOW (V)
0
Notes:
1. Measuring point = Vtrip. See
2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer.
Test Point
Datapath
Min.
–0.3
–0.3
–0.3
–0.3
V
VIL
Max.
0.8
0.8
0.8
0.8
V
Table 2-16 on page 2-17
35 pF
Input HIGH (V)
Min.
V
2
2
2
2
3.3
VIH
Enable Path
Max.
Test Point
3.6
3.6
3.6
3.6
V
R = 1 k
for a complete table of trip points.
Max.
VOL
0.4
0.4
0.4
0.4
V
R e visio n 8
Measuring Point* (V)
VOH
Min.
2.4
2.4
2.4
2.4
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
V
1.4
mA mA
I
OL
2
4
6
8
HZ
I
OH
ZH
2
6
4
8
/ t
/ t
LZ
HZ
LZ
ZHS
Max.
/ t
mA
/ t
I
OSL
25
25
51
51
ZL
ZH
/ t
3
ZL
/ t
/ t
ZLS
ZHS
/ t
ZLS
C
Max.
LOAD
I
mA
OSH
27
27
54
54
10
3
(pF)
µA
I
IL
10
10
10
10
1
4
I
µA
IH
10
10
10
10
2
4

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