A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 52

FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part Number
A3PN125-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN125-ZVQG100

Processor Series
A3PN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Delay Time
1.02 ns
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ProASIC3 nano DC and Switching Characteristics
Figure 2-10 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
2- 38
Enable
Preset
Data
CLK
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
B
A
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive-Edge Triggered
C
D
E
DFN1E1P1
PRE
D
Q
E
Y
R e visio n 8
Array
Core
Data_out
G
H
K
F
J
I
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive-Edge Triggered
D
E
E
D
DFN1E1P1
DFN1E1P1
PRE
PRE
L
Q
Q
DOUT
EOUT

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