A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 23

FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part Number
A3PN125-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN125-ZVQG100

Processor Series
A3PN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Delay Time
1.02 ns
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software.
The power calculation methodology described below uses the following variables:
Methodology
Total Power Consumption—P
Total Static Power Consumption—P
Total Dynamic Power Consumption—P
Global Clock Contribution—P
Sequential Cells Contribution—P
P
P
P
P
N
N
P
P
N
on page
N
page
F
N
P
P
N
sequential cell is used, it should be accounted for as 1.
α
F
CLK
AC1
CLK
TOTAL
STAT
DYN
STAT
DYN
CLOCK
S-CELL
INPUTS
OUTPUTS
SPINE
ROW
S-CELL
S-CELL
1
is the toggle rate of VersaTile outputs—guidelines are provided in
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in
page
Enable rates of output buffers—guidelines are provided for typical applications in
page
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-13 on page
design.
, P
is the global clock signal frequency.
is the global clock signal frequency.
2-11.
is the total dynamic power consumption.
= P
is the total static power consumption.
= P
is the number of VersaTile rows used in the design—guidelines are provided in
AC2
= P
is the number of global spines used in the user design—guidelines are provided in
= (P
= N
is the number of VersaTiles used as sequential modules in the design.
2-11.
is the number of I/O input buffers used in the design.
is the number of VersaTiles used as sequential modules in the design. When a multi-tile
2-11.
2-11.
CLOCK
DC1
is the number of I/O output buffers used in the design.
, P
STAT
S-CELL
AC1
AC3
+ N
+ P
+ P
+ N
, and P
INPUTS
* (P
DYN
S-CELL
SPINE
AC5
2-11. The calculation should be repeated for each clock domain defined in the
AC4
* P
*P
+ P
+
DC2
AC2
are device-dependent.
α
C-CELL
1
TOTAL
+ N
CLOCK
+ N
/ 2 * P
OUTPUTS
ROW
S-CELL
+ P
AC6
STAT
*P
NET
R e v i s i o n 8
) * F
AC3
DYN
* P
+ P
CLK
+ N
DC3
INPUTS
S-CELL
+ P
* P
OUTPUTS
AC4
) * F
CLK
+ P
Table 2-12 on page
MEMORY
ProASIC3 nano Flash FPGAs
+ P
PLL
Table 2-12 on
Table 2-13 on
Table 2-12 on
2-11.
Table 2-12
2 -9

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