A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 81

FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part Number
A3PN125-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN125-ZVQG100

Processor Series
A3PN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Delay Time
1.02 ns
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 2-34 • FIFO FULL Flag and AFULL Flag Assertion
Figure 2-35 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
Figure 2-36 • FIFO FULL Flag and AFULL Flag Deassertion
(Address Counter)
(Address Counter)
(Address Counter)
AEMPTY
WA/RA
EMPTY
WCLK
FULL
AFULL
WA/RA
WCLK
RCLK
RCLK
WA/RA
AFULL
WCLK
FULL
MATCH (FULL)
(EMPTY)
MATCH
NO MATCH
1st Rising
After 1st
Edge
Write
1st Rising
After 1st
Read
Edge
NO MATCH
NO MATCH
2nd Rising
t
NO MATCH
CYC
After 1st
Edge
Write
NO MATCH
1st Rising
After 2nd
Read
Edge
NO MATCH
t
RCKEF
R e v i s i o n 8
t
WCKF
t
CKAF
NO MATCH
NO MATCH
Dist = AFF_TH
NO MATCH
NO MATCH
t
WCKFF
ProASIC3 nano Flash FPGAs
t
CKAF
MATCH (FULL)
t
Dist = AEF_TH + 1
CKAF
Dist = AFF_TH – 1
2- 67

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